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Myriad 2 chip for hackers / creators

Will the Myriad 2 SoC ever be released for hackers / creators in order to integrate into their own PCBs?


  • 18 Comments sorted by Votes Date Added
  • edited October 2017 Vote Up1Vote Down

    We have a MA2450 based reference design of our own design. We will use it to work with our partners going forward rather than building solutions against the Movidius reference design.

    If there is sufficient interest, we may release this to the larger hacker/maker community. We are happy to open the design to the extent we can.

    Movidius has not show an interest in supporting an "open" design so we have to assume anyone using this would still have to get a Movidius license.

    Tegra and NVidia designs, although they are open, are not suitable for <2 watt design profiles. Sure hope we can strike the right deal with Movidius to open the design to makers.

  • @SubZero The Myriad SoC is available for purchase. Please contact us at for more information.

  • Thanks, Tome. :) Have followed this up.

  • Not getting any love from the contacts page. :( That's the second time I've asked a basic question via the 'Contacts' form and received no answer. :(

  • I asked about basic information on MyriadX and got nothing.
    I just wanted to know how this fit into a workflow. It was on the front page of Intels website and said it would do lots of things. I even tweeted to the VP of sales asking how this works.
    As time passed I have deduced its a chip with no pin-out no power requirement. No spec of any kind does it have driver?
    What is going on?
    If I sound frustrated I am.
    I feel like there is a good ole boys club with Movidus and someone.
    I really don't want to tie my boat to an NVidias chipset but I am not seeing a lot of options here. They have documentation and demo code that makes sense. Just have to pay a premium for that stuff. No wonder Elon went with AMD to make a chip.

  • @chicagobob123 I feel your pain. Unfortunately, Movidius seems to be neglecting a movement which is literally worth billions of dollars. I'm not sure why this forum even exists based on the fact that it's next to impossible to get access to a technical reference, and the chance to reflow a Myriad BGA onto a custom PCB seems like an impossible dream.

    The ability to do anything meaningful with a Myriad SoC via the NCS is also currently severely limited by the SDK, and not giving access to hardware references has completely blocked any useful development on this platform. This is frustrating, as the Myriad solves a final problem which I needed to solve.

    The Myriad SoC has moved onto the next generation (Myriad X), so they could at least give us access to the last generation of technology. Intel is usually super good with releasing detailed hardware programmers references - not so much in this case.

  • Last post from me on this. "Intel is usually super good with releasing detailed hardware programmers references - not so much in this case." I agree completely and am disappointed. No support for Tensor flow when Myriad 2 had it. No RCNN of YOLO support? Single item detection has a very limited scope.
    As a developer I don't have the people or want to figure out the timing diagrams of a chip to understand how to get the best performance for its internal algorithms. They state the chip already DOES all kinds of magical things in the advert. Why do we need to reinvent the wheel. How did they get their results?
    And like everyone in this Image classification gold rush we are all under deadline hell to get going on a solution. Enough talk. 3rd quarter is almost over back to work

  • Still no love from Movidius. Well, to be fair, I actually got a "No, you can't have anything from us, so don't bother asking unless you have a tree which supplies infinite cash sitting outside your window".

    Intel, show some love to the rest of us, please.

  • I think I'll move onto Nvidia's Tegra SoCs - no point in attempting to do anything meaningful with a company which flatly refuses the release of reference manuals to engineers for use with their hardware. Movidius would probably be the first company that has actually refused to release a hardware reference manual. I can actually go to Nvidia's developers portal and access a 2600 page technical reference manual for their Tegra series, access board reference designs and hardware, a rich set of developer libraries.

  • @victorv A reference design is only a part of solution. Gaining access to technical references (or more advanced SDKs), or the Myriad VPUs for design prototyping, is the biggest uphill battle with Movidius. They could at least come halfway to the table and provide basic references for the mechanical and electrical characteristics and release the VPUs for purchase via distributor networks (Arrow, RS, etc).

  • @SubZero - our current plan is to package a binary blob for an interface which will be open source so you can at least perform all major operations. The key problem is being able to compile your own code directly for Myriad2 - we can't do that without sublicensing Movidius' tools or repackaging it into an acceptable form or having the user license the tools and drop it into our tool chain.

    We will open source the hardware design for the Myriad2 main-board. VPUs are already available from a few major distributors.

  • @victorv The VPUs are accessible from distributors? Which ones? I contacted Movidius a few weeks back and they said that it's not possible to get access to the VPUs in prototype batches, without a major license.

    I would love to get access to these VPUs and reference designs for a prototype we are working on. Movidius seems to be moving in the right direction with their releases of the SDK, so hopefully access to hardware follows.

    When do you plan on opensourcing your hardware design?

  • @victorv I think I may have tracked the VPU down on Arrow.

  • @victorv Is the LPDDR3 onboard the Myriad SoC, or is it accessible through LPDDR3 EMC? Also, they mention 2MB of memory onboard - is this Flash?

  • Oops, I just answered my own questions - LPDDR3 onboard the SoC (128MB / 512MB) and 2MB of CMX SRAM for use by the SHAVEs (or LEON cores, etc). I like that the 256KB of SHAVE L2 can be partitioned into 16KB chunks, and allocated to the SHAVE LSUs independently.

    How much control over the SHAVE I/D caches do we have? Can code be loaded directly into a SHAVE I-cache? Is the CMX DMA controller intelligent - can it be programmed to transfer a non-contiguous block of data into the CMX SRAM, ie, a rectangular block of data from DDR?

  • @SubZero - I can't share any details about MA2x50 which is covered under NDA. That said, their public information is clear about the DDR and CMX sizes. The other details are under NDA.

    From an SDK / development perspective, we will provide a higher level abstraction. Bit-banging interfaces will require you to get an MDK license and deal with all the low-level driver and hardware issues. This would put the kit out of reach for most people so we are looking at providing the right abstraction level.

  • @chicagobob123 Recently got the NCS and yolo/tinyYolo is what I am also looking for.
    There is a thread on ncs forum about a tinyYolo example, which is also available on git
    With a little trouble I was able to run it at 4-5 fps on a 720p webcam
    I didn't like the accuracy but that's all a matter of using right weights I believe.

    Hoping that MyriadX would be a lot more faster than this. However current performance as well shouldn't be too bad to start with?

  • "thepaintedsnipe" How many items are in your inference set? How many items can you identify simultaneously.

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